General  UNIBUS  information UNIBUS

PDP11 BUS handbook

The UNIBUS consists of groups of wires that carries specific electrical signals to which all modules in PDP-11 UNIBUS-based computer are connected. The UNIBUS is a transmission medium that interconnects the so-called bus devices of the system. As the transmission lines in the UNIBUS have a characteristic impedance, both ends must be properly terminated. This is accomplished by a UNIBUS terminator module, or on the processor module itself.
The wires in the UNIBUS can be classified in 3 groups.

  1. initialization (3 lines)
    Signals on these lines control power-up, power-down, or initialization sequences of the bus devices.
  2. data (38 lines)
    These lines are used for data transfer between the devices.
  3. priority arbitration (15 lines)
    Signals on these lines decide which device will next be allowed to control the data lines.
In total, 56 wires form these 3 groups, along with 64 corresponding ground wires.
For a basic understanding of the operation of the UNIBUS the following topics are explained.


The following names are introduced to understand the operation of the UNIBUS.

Bus segment
A bus segment is the portion of a UNIBUS system between 2 terminators. A system may consist of one or more segments. The number of devices that may be connected to a segment is limited, as is the length of its cable.
Bus repeater
A bus repeater is a device used to connect 2 segments of a multi-segment UNIBUS system. A repeater receives the signals of one segment and retransmits them onto the other segment. Its purpose is twofold. (1) It prevents signal levels from becoming degraded due to the connection of too many devices to a bus. (2) By receiving and then retransmitting all signals going between one segment and the next, it ensures that the proper timing relationship between signals is maintained.
Bus master
The bus master is the device or processor that is currently permitted to use data section of the UNIBUS. Only one device may be master at a given time. Typically, the master uses the data section of the bus to transfer data between itself and another device which is called the "slave". An example is the processor, as master, fetching an instruction from memory (which is always a slave).
Bus slave
The bus slave is the device that communicates with the bus master. Only one device may be the bus slave at a given time.
Some devices may become both master and slave (at different times), while other devices may become only master or only slave.
Bus arbitrator
The bus arbitrator is a logic circuit that compares priorities from devices requesting the use of the data section of the bus in order to determine which device is to be granted control next (that is, become next bus master). The processor, as bus arbitrator, may pass bus control to a Direct Memory Access (DMA) device. The DMA device, as bus master, could then communicate with memory (always as a slave) without processor intervention.
The arbitrator may or may not be part of a processor. There must be one, and only one arbitrator on a UNIBUS. A system may have more than one UNIBUS, each with its own arbitrator.
Bus Request
A request by a master device to use the data section of the bus. The request is sent to the arbitrator on one of 5 signal lines: BR4, BR5, BR6, BR7, and NPR (Non-Processor Request).
Bus Grant
A grant is a signal to the requesting device that it may become next bus master. The grant is sent by the arbitrator on one of 5 signal lines: BG4, BG5, BG6, BG7, and NPG (Non-Processor Grant).
A processor is a bus devices that includes the circuits that control the interpretation and execution of instructions. A processor does not include the UNIBUS, main memory, or peripheral devices. A processor may become master or slave.
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UNIBUS description

The function of the UNIBUS is to allow data to be exchanged between devices as directed by the program. The program is a sequence of instructions as interpreted by the processor. Data is transmitted on the bus either as 16-bit words or as 8-bit bytes. The data exchange is always between a master and a slave. The master determines which device will become slave by putting the address of the desired slave device on the bus. In order to become bus master a device must request and obtain the use of the data section. This request may be made any time the device is ready for a data transfer. Any number of devices may be asserting a request at the same time. The priority scheme implemented by the arbitrator determines which of these requests is honored, that is, which device will obtain the use of the data section when it becomes free. Several devices may be ready to transfer data at the same time. Since only one of these devices can obtain the use of the data section, the other requesting devices have to wait before being allowed to transfer data. If the wait time is too long, some devices may lose data. This wait period is known as latency.
wired-OR lines

Signals on the UNIBUS can be divided into 2 general categories.

The majority of the bus signals use lines that are wired-OR circuits to which the inputs to the bus receivers (green) and the outputs to the bus drivers (purple) are connected. These lines are available along the length of the UNIBUS to any device.

Five UNIBUS signals use lines where the signal is received only by the device that is closest on the line to the origin of the signal. This receiving device, in turn, either re-transmits the signal to the next device on the line, or does not re-transmit the signal ("blocks" the signal). The transmission process continues until either a device blocks the signal or the end if the line is reached. These lines are used only by the arbitrator to grant bus access permission to devices requesting the use of the data section of the bus.

bus access request lines

A priority structure determines which requesting device will use the data section of the bus. The priority is a function of (1) the priority level assigned to the device, and (2) its position on the bus with respect to other devices of the same priority level. All devices, with one exception, may be assigned to one (or more) of 5 hardware priority levels. Each of these levels has a dedicated signal line. Each signal line is driven by all bus devices assigned to the priority level. These 5 lines are called Bus Request lines (NPR, BR7, BR6, BR5, BR4) and are monitored by the arbitrator. A device that requires the use of the data section asserts a request on one of these lines. The arbitrator issues a grant to the highest priority request active. A grant signal informs the requesting device that it may become next bus master. This grant signal is sent on a separate line, NPG, BG7, BG6, BG5, BG4. The level of the grant is the same as that of the request. The arbitrator issues a grant to the first device on the bus assigned to the same priority level as the grant. If this device is requesting the use of the data section, it accepts and acknowledges receipt of the grant. It also blocks further transmission on the grant line. If the device is not requesting the use of the data section, it passes the grant to the next device on the same grant line. This procedure is repeated until a device accepts the grant or until the end of the bus is reached. In the latter case, the grant is cancelled by the arbitrator and the arbitration process is restarted. All devices assigned to a given priority level have higher priority than any device at a lower level. Within a given priority level, the device closest to the arbitrator (origin of grant signal) has the highest effective priority.

An address is the name of a location in memory of a register. A number specifies the location. A UNIBUS device may contain one or more locations. A simple device such as a line clock may contain only one; a memory device may contain thousands. A device may be able to store many words and yet have only 3 or 4 address locations. An example of this is a disk controller. An address location may be used for storage of data or for control of a device.
A PDP-11 16-bit word is divided into a low byte (bits 0-7) and a high byte (bits 8-15). A 16-bit word used for addressing can address a maximum of 32K words (or 64K bytes). However, the top 4096 word locations are reserved for peripheral register addresses, and the user therefore has 28K words for programs. Systems with Memory Management options provide an 18-bit effective memory address which permit addressing up to 124K words of memory for programs.
A device must be bus master to use the address lines. An address put on the address lines by a master is received by all bus devices that are capable of becoming slaves. One of these devices recognizes its address and becomes the slave. The slave does not know which device is master nor where the master is physically located on the bus. The master does not know the physical location of its slave, nor does it need to know. Each external I/O device has an external page address assigned to it. The use of this address on the UNIBUS is defined as part of the PDP-11 I/O page.

Latency is the delay between the time that a device initiates a request and the time that it receives a response. Non-processor request (NPR) or Bus Request (BR) latency is the total time consumed by all the operations that occur between the instant a device makes a request and the moment it becomes bus master. The delay encountered is a function of current bus activity, the types of other devices in the system, and the arrangement or configuration of the equipment along the bus. Maximum tolerable latency is the longest time a device can wait for service before losing data. The service time is measured from the assertion of the request by the device to the time that the requested data transfer is complete.
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Arrangement of devices on the UNIBUS

The arrangement of devices on the UNIBUS is a function of the following 4 factors.

  1. Any device can communicate with any other device on the data section of the bus. Physical position of the device is not important to its ability to communicate on the UNIBUS.
  2. Grants are issued by the arbitrator and received and re-issued by each device of the same level. All devices capable of becoming bus master must be on the same side of the arbitrator. In reality, the arbitration is on the processor module. Most bus devices are located on one side of the CPU module.
  3. The maximum tolerable latency for each device must not be exceeded. This depends on
    1. the priority level assigned to the device,
    2. its position on its grant signal line relative to other devices of the same priority level,
    3. the effect on the bus of all other devices at their priority levels,
    4. the length of the bus.
  4. The maximum length of the UNIBUS should not exceed 15.24 meter (50 ft). A bus repeater can drive an additional 50 ft. A bus repeater can also be required if the maximum number of devices on a segment is exceeded (bus loading).
UNIBUS configuration
A typical UNIBUS configuration is shown in the picture. The bus is terminated at both ends.

The processor module terminates one end of the bus, a terminator module terminates the other end.

Various devices such as memory, peripheral controllers, and I/O devices are placed between these modules.
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Protocol on the UNIBUS

The UNIBUS protocol defines the procedures that are used for communication on the bus. Communication between devices is in the form of transactions. A transaction is a sequence of signals that complete a logical unit of activity on the UNIBUS. There are 3 types of transactions, priority arbitration, data transfer and initialization. Each of these transaction types occurs on a separate section on the UNIBUS. This allows simultaneous priority arbitration and data transfer transactions. For example, the next master can be selected while the current master executes its data transfer.

Priority arbitration transaction
Priority arbitration determines which device will obtain control of the bus. The arbitration selects the device to become the next bus master when the current master releases the data section of the bus. Any number of devices may request the use of the data section at one time. The one device that is selected to be bus master is the one with the highest effective priority. The highest priority device grant is the non-processor grant (NPG). It is used by a device that does not require processor time. It may be used by devices only for data transfers that do not require interrupts. When requested, an NPG grant is issued on this level. The NPG is issued by the arbitrator for an NPR request. NPR is the highest request level. More than one device may be connected to the UNIBUS at the NPR level of priority. In the case of a tie for an NPR request, the device closest to the arbitrator is granted the NPG (on the NPG line).
The CPU program execution priority (PRI) varies from 0 to 7. The UNIBUS arbitrator grants use of the bus to non-CPU devices by the following rules.
  1. At any time when an NPR is received, assert NPG. A controller may do direct memory access data transfers at any time.
  2. When the CPU is between instructions, then
    • If PRI < 7 and BR7 is received, assert BG7
    • If PRI < 6 and BR6 is received, assert BG6
    • If PRI < 5 and BR5 is received, assert BG5
    • If PRI < 5 and BR4 is received, assert BG4
    The CPU will accept interruptions from a controller whose priority is greater than the current program execution priority of the CPU.
Data transfer
A data transfer is the transmission of data between a master and a slave. This transfer can occur without processor intervention or supervision.
The device that has been granted next bus master waits for the UNIBUS to be released by the current bus master. When a device becomes bus master, it causes one or more words of data to be transferred between itself and a slave device. The particular salve and the direction of the transfer are determined by the information issued by the bus master onto the UNIBUS. When the transfer is complete, the master releases the bus, at which time a new device may assume mastership. A device in control of the bus can transfer data at the maximum rate allowed by the combination of the master, the slave, and the bus.
There are 4 types of data transfer transactions on the UNIBUS, data-in, data-out, read/modify/write, and interrupt.
Data-in is the transfer of one word from a slave to a master.
Data-out is the transfer of one word from a master to a slave. Data-out, byte is the transfer of one byte from a master to a slave.
Read/modify/write is a transaction in which data is transferred from a slave location to a master, modified by the master, and transferred back to the same slave location. A read/modify/write consists of a data-in, pause followed by a data-out or by a data-out byte. The data-in, pause is identical to the data-in, however, it informs the slave that a data-out transaction to the same location will follow the data-in. If the slave is a destructive readout device (for example core memory), it automatically restores the data after the data-in. After a data-in, pause, the slave might not restore the data, but may wait for the modified data from the following data-out.
An interrupt transaction is the transfer of one word, the "interrupt vector", from the master to the CPU.
The initialization section of the UNIBUS continuously monitors the AC power input to the bus power supplies. It also controls the orderly power-up and power-down of all bus devices. Individual devices may be initialized under program control. Bus initialization stops all bus operations and puts all bus devices in a well defined state.
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UNIBUS signals

All activity on the UNIBUS is asynchronous and depends on interlocked control signals. In every case, a control signal transmitted is acknowledged by the receiver of that signal.

    D A T A   T R A N S F E R   S E C T I O N
AddressA <17:00>18Selects slave device and/or memory addresslow
DataD <15:00>16Information transferlow
ControlC0, C12Type of data transferlow
Master syncMSYN1Timing control for data transferlow
Slave syncSSYN1Timing control for data transferlow
ParityPA, PB2Device parity errorlow
    P R I O R I T Y   A R B I T R A T I O N   S E C T I O N
Bus RequestBR4, BR5, BR6, BR74Requests use of bus (usually for interrupts)low
Bus GrantBG4, BG5, BG6, BG74Grants use of bus (usually for interrupts)high
Non-Processor RequestNPR1Requests use of bus for data transferlow
Non-Processor GrantNPG1Grants use of bus for data transferhigh
Selection acknowledgeSACK1Acknowledges grantlow
Bus BusyBBSY1Indicates that the data section is in uselow
    I N I T I A L I Z E   S E C T I O N
InitializeINIT1System resetlow
AC lowAC LO1Power monitoringlow
DC lowDC LO1Power monitoringlow

All transactions on the priority arbitration and on the data transfer section are interlocks dialogs between devices. The requesting devices and the arbitrator communicate on the priority arbitration section. The bus master and the bus slave communicate on the data transfer section. The signals that delimit or establish the boundaries for data operations are for data transfer MSYN and SSYN, and for interrupt INTR and SSYN. The signals that delimit priority arbitration are [NPR, NPG] or [BRn, BGn], SACK, BBSY.

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